1. Field of the Invention
The present invention relates to a semiconductor memory device, having multi-bank, with overdriven sense amplifiers and a stabilized power-supply circuit of source follower type for use in a semiconductor device such as a memory device.
2. Description of the Related Art
FIG. 21 shows a circuit associated with a sense amplifier 10 of a prior art synchronous dynamic random access memory device (SDRAM).
The sense amplifier 10 is activated by a voltage between power supply voltages VP and VN provided from sense amplifier driving circuit 11. In the circuit 11, PMOS transistor 12 and NMOS transistors 13 through 15 are connected in series, a sense amplifier control signal C0 from a control circuit (not shown) is provided to the gate electrode of the NMOS transistor 15, and a signal *C0 complementary to this signal (`*` denotes active low) is provided to the gate electrodes of the transistor 12 through 14. In a case where the sense amplifier control signals C0 and *C0 are low and high, respectively, the transistors 13 and 14 are on, and transistors 12 and 15 are off, whereby a voltages Vii/2 are provided through the transistors 13 and 14 as VP and VN to the sense amplifier 10, and the sense amplifier 10 is inactive. In this state, transfer gates 16 and 17 are turned on, and a pre-charge circuit 18 is turned on with pre-charge signal PR activating, whereby bit lines BL01, BL02, *BL01, and *BL02 are pre-charged up to the voltage Vii/2. The voltage Vii/2 is applied to the cell plate of the capacitor of a memory cell 19.
For example, when data is read out from the memory cell 19 storing "HIGH", a word line WL0 is raised and a positive charge moves from the memory cell 19 to the bit line BL01, whereby a voltage difference of approximately 100 through 200 mV occurs between the bit lines BL01 and *BL01. In order to activate the sense amplifier 10 faster, in response to the change in a row address, as shown in FIG. 22, a power supply voltage VH rises from Vii to Vjj in order to overdrive a bit line. For example, the voltages Vii and Vjj are 1.5V and 2.0V, respectively.
Next, the sense amplifier control signals C0 and *C0 transit to a high and a low, respectively, transistors 12 and 15 are turned on, transistors 13 and 14 are turned off, and the voltages VH and 0V are provided as the VP and VN through the transistors 12 and 15, respectively, to the sense amplifier 10. Thereby, the sense amplifier 10 is activated to amplify the voltage difference between the bit lines BL01 and *BL01. After the bit lines BL01 and *BL01 have fully swung between the voltages Vii and 0V by this amplification, the voltage VH is lowered to the voltage Vii.
When the reading has completed, the word line WL0 goes low, and then, the sense amplifier control signals C0 and *C0 go low and high, respectively, and the VP and VN both return to the voltage Vii/2, whereby the sense amplifier 10 becomes inactive. Further, the pre-charge circuit 18 is turned on with the pre-charge signal PR activating, and the bit line voltage is reset to Vii/2.
In a prior art SDRAM equipped with a plurality of banks, the voltage VH is commonly provided to sense amplifier driving circuits of the respective banks. While performing processing of the banks before being switched, the bank after being switched is processed in parallel. Therefore, as shown in FIG. 23, for example, when banks 0 through 3 are switched successively, the power supply voltage VH does not drop to the voltage Vii but maintains the voltage Vjj.
As a result, current is consumed needlessly, and also, since the high voltage period becomes longer than necessary, deterioration of transistor characteristics is accelerated.
On the other hand, pre-charge by the pre-charge circuit 18 in FIG. 21 is rapidly performed primarily with the short circuit of the bit lines BL02 and *BL02, and supplementary pre-charge from the supply line at a voltage Vii/2 is gradually performed since Vii/2 is generated by voltage dividing with resistors and a current flows through the resistor. Therefore, when a reading is performed again from the bank 0 after the bank 3, and this reading is from the same bit line pair whose voltage difference was amplified at the last reading from the bank 0, as shown in FIG. 23, pre-charge voltage Vpr2 becomes higher than the normal pre-charge voltage Vpr1=Vii/2. A voltage difference .DELTA.V between a bit line pair after being read thereon from a memory cell and before being amplified depends on a pre-charged voltage Vpr of the bit line pair, and is expressed by the following equation. EQU .DELTA.V=(Vsn-Vpr).multidot.Cs/(CBL+Cs)
where, Cs is the capacity of the memory cell, CBL is the parasitic capacity of the bit line pair, and Vsn is the voltage of the storage node 191 before the reading.
As clear from this equation, if the Vpr rises under Vsn being constant, .DELTA.V decreases. That is, the voltage difference .DELTA.V2 in FIG. 23 between a bit line pair becomes smaller than the normal .DELTA.V1.
If the voltage difference .DELTA.V between a bit line pair becomes smaller, since the margin of operating without error reduces in regard to the sense amplifiers, the sense amplifier 10 may erroneously operate due to variance in the element characteristics of the sense amplifier 10. Furthermore, a refresh cycle time must be shortened to maintain the storage node voltage Vsn high, resulting in an increase of a wasteful current.
There is another cause to raise the pre-charged voltage Vpr if a power supply circuit of source follower type is employed for driving sense amplifiers even if the above-described overdriving of sense amplifiers is not used.
That is, if a NMOS transistor is employed at the output stage in a power supply circuit for the sense amplifiers, letting the voltages of the drain, gate and source electrodes thereof be an external power supply voltage, a constant VG and the output voltage Vii of the power supply circuit, respectively, the relation Vii=VG-Vth approximately holds, where Vth is a threshold voltage of the NMOS transistor. However, since the current consumption at the sense amplifier is zero after the voltage between a bit line pair is fully swung by the sense amplifier and a little current flows through the NMOS transistor, Vii rises and thereby the precharge voltage Vii/2 goes up, resulting in an increase in a wasteful current.